The present specification relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present specification relates to a transistor having a specialized source or drain junction and a method of manufacturing it.
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing transistor density on ICs has been a principal focus of the microelectronics industry. An ultra-large scale integrated circuit can include over 1 million transistors. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices.
In bulk semiconductor-type devices, transistors, such as, MOSFETs are built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (or thickness of the depletion layer below the inversion channel) must be scaled down to achieve superior short channel performance.
According to conventional complimentary metal oxide semiconductor (CMOS) fabrication techniques, the reduction of the depletion layer thickness is realized by a super-steep retrograded well (SSRW) ion implantation process. However, this process is limited by the diffusion of dopant atoms during subsequent thermal processes (e.g., annealing). The ion implantation process can generally only achieve an 80-nanometer or larger body thickness for a transistor. Thus, conventional fabrication techniques for bulk semiconductor type-devices cannot create transistors with a body thickness less than 80 nm.
Accordingly, bulk semiconductor-type devices can be subject to disadvantageous properties due to the relatively large body thicknesses. These disadvantageous properties include less than ideal sub-threshold voltage rolloff, short channel effects, and drain induced barrier lowering. Further still, bulk semiconductor-type devices can be subject to further disadvantageous properties such as high junction capacitance, ineffective isolation, and low saturation current. These properties are accentuated as transistors become smaller and transistor density increases on ICs.
Conventional SOI-type devices include an insulative substrate attached to a thin film semiconductor substrate which contains transistors similar to the MOSFET described with respect to bulk semiconductor-type devices. The transistors have superior performance characteristics due to the thin film nature of the semiconductor substrate and the insulative properties of the insulative substrate. The superior performance is manifested in superior short channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current. SOI transistors do not typically include high-k gate dielectric materials.
According to one example of an SOI-type device, a partially-depleted SOI MOSFET has advantages (e.g., reduced source/drain junction capacitance, latch-up free, etc.) over bulk-type MOSFETs. However, partially depleted SOI MOSFETs as well as other types of SOI devices are susceptible to floating-body effect (FBE). For example, a major drawback for the use of SOI technology in memory is related to instability caused by floating-body effect.
Floating-body effect is caused by impact ionization in the channel region during on-state operation. The impact ionization typically occurs near the drain side of the channel region. Majority carriers (e.g., holes in an N-channel MOSFET) accumulate in the body of the SOI transistor.
The accumulation of carriers increases a potential between the channel region and the drain region. The increased potential reduces the threshold voltage of the transistor, thereby adversely affecting the stability and power consumption of the transistor. A reduced threshold voltage for the transistor increases the off-state current and on-state current of the transistor. Ideally, transistors are designed to suppress or avoid floating-body effect if possible.
Complex transistor designs are often required to reduce floating body effect. For example, substrate contact schemes, such as a low barrier body contact (LBBC) scheme, have been utilized to provide a substrate contact for substrate current collection for the SOI substrate, thereby reducing the floating-body effect. However, providing substrate contacts on an SOI substrate requires space and can add process complications.
Thus, there is a need for a method of manufacturing thin film, partially depleted MOSFET which has advantages over conventional bulk type devices. Further still, there is a need for a method of manufacturing a transistor which has superior short-channel performance, near ideal subthreshold swing, and high saturation current and yet is not susceptible to floating body effect. Even further still, there is a need for a process for making a thin film transistor which has a specialized source/drain region that reduces floating body effect.
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The method includes providing a gate structure between a source location and a drain location on a semiconductor film, providing a source region at the source location and a drain region at the drain location, and providing an angled dopant implant. The angled dopant implant forms an amorphous region in the film. The method further includes annealing the film to recrystallize the amorphous region.
Still another exemplary embodiment relates to a method of manufacturing an SOI transistor having reduced floating body effects. The method includes steps of providing at least part of a gate structure on a top surface of a semiconductor substrate and doping a deep source region and a deep drain region in a semiconductor substrate. The gate structure includes a pair of spacers. The method further includes doping the entire deep source region under one of the spacers while not doping the deep drain region under the other of the spacers, and annealing the semiconductor substrate.
Still another exemplary embodiment relates to a method of doping a source region and/or a drain region for a transistor. The transistor includes a gate structure disposed over a channel in a substrate, a source region heavily doped with dopants of a first conductivity type, and a drain region heavily doped with dopants of the first conductivity type. The method includes amorphizing the substrate at an angle with dopants of the first conductivity type. The method further includes annealing the substrate. An abrupt junction in the lateral direction for the source region or the drain region is formed. The source region and the drain region are asymmetrical.